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CY2DP3120 - Differential Clock/Data Fanout Buffer

General Description

The CY2DP3120 is a low-skew, low propagation delay 1-to-20 differential fanout buffer targeted to meet the requirements of high-performance clock and data distribution applications.

Key Features

  • Twenty ECL/PECL differential outputs.
  • One ECL/PECL compatible differential or single-ended clock inputs.
  • One HSTL compatible differential or single-ended clock inputs.
  • Hot-swappable/-insertable.
  • 50 ps output-to-output skew.
  • 150 ps device-to-device skew.
  • 500 ps propagation delay (typical).
  • 1.4 ps RMS period jitter (max. ).
  • 1.5 GHz Operation (2.7 GHz max. toggle frequency).
  • PECL mode supply range: VCC = 2.5V±.

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Full PDF Text Transcription for CY2DP3120 (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for CY2DP3120. For precise diagrams, tables, and layout, please refer to the original PDF.

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www.DataSheet4U.com FastEdge™ Series CY2DP3120 1:20 Differential Clock/Data Fanout Buffer Features • Twenty ECL/PECL differential outputs • One ECL/PECL compatible differential or single-ended clock inputs • One HSTL compatible differential or single-ended clock inputs • Hot-swappable/-insertable • 50 ps output-to-output skew • 150 ps device-to-device skew • 500 ps propagation delay (typical) • 1.4 ps RMS period jitter (max.) • 1.5 GHz Operation (2.7 GHz max. toggle frequency) • PECL mode supply range: VCC = 2.5V± 5% to 3.3V±5% with VEE = 0V • ECL mode supply range: VE E = –2.5V± 5% to –3.3V±5% with VCC = 0V • Industrial temperature range: –40°C to 85°C • 52-pin 1.